ISL8204M 查看數據表（PDF） - Renesas Electronics
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ISL8204M Datasheet PDF : 19 Pages
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ISL8204M, ISL8206M
4.0
3.5
5.0V
3.0
3.3V
2.5
0.6V
2.0
1.5V 2.5V
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
LOAD CURRENT (A)
FIGURE 28. POWER LOSS vs LOAD CURRENT (12VIN)
Thermal Considerations
Experimental power loss curves along with JA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. The power loss and derating curves apply for both
ISL8206M, and ISL8204M. The loss at 4A can be found by
tracing the power loss curve up at the load current of 4A. In
actual applications, other heat sources and design margins
should be considered.
Package Description
The structure of ISL8204M, ISL8206M belongs to the Quad
Flat-pack No-lead package (QFN). This kind of package has
advantages, such as good thermal and electrical conductivity, low
weight and small size. The QFN package is applicable for surface
mounting technology and is being more readily used in the
industry. The ISL8204M, ISL8206M contains several types of
devices, including resistors, capacitors, inductors and control ICs.
The ISL8204M, ISL8206M is a copper lead-frame based package
with exposed copper thermal pads, which have good electrical and
thermal conductivity. The copper lead frame and multi-component
assembly is overmolded with polymer mold compound to protect
these devices.
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown in the package outline
drawing L15.15x15 on page 18. The module has a small size of
15mmx15mmx3.5mm. Figure 30 shows typical reflow profile
parameters. These guidelines are general design rules. Users can
modify parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8204M, ISL8206M is a lead-frame footprint,
which is attached to the PCB using a surface mounting process.
The PCB layout pattern is shown in the Package Outline Drawing
L15.15x15 on page 18. The PCB layout pattern is essentially 1:1
with the QFN exposed pad and I/O termination dimensions,
except for the PCB lands being a slightly extended distance of
0.2mm (0.4mm max) longer than the QFN terminations, which
allows for solder filleting around the periphery of the package.
This ensures a more complete and inspectable solder joint. The
FN6999 Rev 4.00
October 28, 2014
7
6
5
4
5.0V
3.3V
2.5V
3
1.5V
0.6V
2
1
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 29. DERATING CURVE (12VIN)
thermal lands on the PCB layout should match 1:1 with the
package exposed die pads.
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under
the thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 ounce copper.
Although adding more vias (by decreasing via pitch) will improve
the thermal performance, diminishing returns will be seen as
more and more vias are added. Simply use as many vias as
practical for the thermal land size and your board design rules
allow.
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mil to 3mil) standoff height. The solder
paste stencil design is the first step in developing optimized,
reliable solder joints. Stencil aperture size to land size ratio
should typically be 1:1. The aperture width may be reduced
slightly to help prevent solder bridging between adjacent I/O
lands. To reduce solder paste volume on the larger thermal
lands, it is recommended that an array of smaller apertures be
used instead of one large aperture. It is recommended that the
stencil printing area cover 50% to 80% of the PCB layout pattern.
A typical solder stencil pattern is shown in the Package Outline
Drawing L15.15x15 on page 18. The gap width between pad to
pad is 0.6mm. The user should consider the symmetry of the
whole stencil pattern when designing its pads. A laser cut,
stainless steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release
which reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a "brick like" paste
deposit that assists in firm component placement. A 0.1mm to
0.15mm stencil thickness is recommended for this large pitch
(1.3mm) QFN.
Page 15 of 19
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