ISL8204M 查看數據表（PDF） - Renesas Electronics
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ISL8204M Datasheet PDF : 19 Pages
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ISL8204M, ISL8206M
Reflow Parameters
Due to the low mount height of the QFN, "No Clean" Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
QFN. The profile given in Figure 30 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
300 PEAK TEMPERATURE +230°C~+245°C;
TYPICALLY 60s-70s ABOVE +220°C
250 KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
200 SLOW RAMP (3°C/s MAX)
AND SOAK FROM +100°C
TO +180°C FOR 90s~120s
150
100
RAMP RATE 1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 30. TYPICAL REFLOW PROFILE
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
October 28, 2014
FN6999.4
Updated Storage Temperature Range, TSTG page 5 from “-40°C to +155°C” to “-55°C to +155°C”.
Replaced Note 2 with the following: “These Intersil plastic packaged products are RoHS compliant by EU
exemption 7C-I and employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3) termination finish which is compatible with both SnPb and Pb-free soldering
operations. Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet
or exceed the Pb-free requirements of IPC/JEDEC J STD-020.”
Updated Products verbiage to About Intersil verbiage on page 17.
June 19, 2012
FN6999.3
On page 9:
Changed conditions for Output Ripple Performance waveforms on from:
TA = +25C, VIN = 12V, PVCC = 12V, CIN = 220µFx1, 10µF/Ceramic x 2, COUT = 330µF (ESR = 10mΩ),
22µF/Ceramic x 3 IOUT = 0, 4, 6A
To:
TA = +25C, VOUT = 1.5V, CIN = 220µFx1, 10µF/Ceramic x 2, COUT = 47µF/Ceramic x 8
Removed 2.5V OUTPUT RIPPLE and 3.3V OUTPUT RIPPLE waveforms
Replaced Figures 13 and 14. Changed Figure 13 caption from “1.2V OUTPUT RIPPLE” to “OUTPUT VOLTAGE
RIPPLE AT VIN = 5V”. Changed Figure 14 caption from “1.5V OUTPUT RIPPLE” to “OUTPUT VOLTAGE RIPPLE AT
VIN = 12V”
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For additional products, see www.intersil.com/en/products.html
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6999 Rev 4.00
October 28, 2014
Page 16 of 19
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