ISL8204M 查看數據表（PDF） - Renesas Electronics
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ISL8204M Datasheet PDF : 19 Pages
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ISL8204M, ISL8206M
controls and limits the current surge. The value of the input
capacitor can be calculated by Equation 5:
CIN = -I-I--N------V---------t
(EQ. 5)
Where:
CIN is the input capacitance (µF)
IIN is the input current (A)
t is the turn on time of the high-side switch (µs)
V is the allowable peak-to-peak voltage (V)
In addition to the bulk capacitance, some low Equivalent Series
Inductance (ESL) ceramic capacitance is recommended to
decouple between the drain terminal of the high-side MOSFET
and the source terminal of the low-side MOSFET. This is used to
reduce the voltage ringing created by the switching current
across parasitic circuit elements.
Output Capacitors
The ISL8204M, ISL8206M is designed for low output voltage
ripple. The output voltage ripple and transient requirements can
be met with bulk output capacitors (COUT) with low enough
Equivalent Series Resistance (ESR). COUT can be a low ESR
tantalum capacitor, a low ESR polymer capacitor or a ceramic
capacitor. The typical capacitance is 330µF and decoupled
ceramic output capacitors are used. The internally optimized
loop compensation provides sufficient stability margins for all
ceramic capacitor applications with a recommended total value
of 400µF. Additional output filtering may be needed if further
reduction of output ripple or dynamic transient spike is required.
Layout Guide
To achieve stable operation, low losses and good thermal
performance some layout considerations are necessary.
3.5
3.0
2.5
3.3V
1.5V
2.0
0.6V
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
LOAD CURRENT (A)
FIGURE 26. POWER LOSS vs LOAD CURRENT (5VIN)
• The ground connection between pin 11 and pins 1 through 4
should be a solid ground plane under the module.
• Place a high frequency ceramic capacitor between (1) VIN and
PGND (pin 11) and (2) PVCC and PGND (pins 1 through 4) as
close to the module as possible to minimize high frequency
noise.
• Use large copper areas for a power path (VIN, PGND, VOUT) to
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
• Keep the trace connection to the feedback resistor short.
• Avoid routing any sensitive signal traces near the PHASE node.
CPVCC
PGND
VIN
RFB
VOUT
CIN
COUT1
(DECOUPLE)
PGND
FIGURE 25. RECOMMENDED LAYOUT
7
6
5
3.3V
4
1.5V
0.6V
3
2
1
0
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 27. DERATING CURVE (5VIN)
FN6999 Rev 4.00
October 28, 2014
Page 14 of 19
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