ISL8204M 查看數據表（PDF） - Renesas Electronics
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ISL8204M Datasheet PDF : 19 Pages
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ISL8204M, ISL8206M
controlled, however, it is affected by the step size of the output and
the value of the output capacitors, as well as the internal error
amp compensation. Therefore, it is possible to trip the overcurrent
with in-rush current, in addition to the normal load and ripple
considerations.
Figure 23 shows the output response during a retry of an output
shorted to PGND. At time t0, the output has been turned off due to
sensing an overcurrent condition. There are two internal soft-start
delay cycles (t1 and t2) to allow the MOSFETs to cool down in order
to keep the average power dissipation in retry at an acceptable
level. At time t2, the output starts a normal soft-start cycle, and the
output tries to ramp. If the short is still applied and the current
reaches the ISET trip point any time during the soft-start ramp
period, the output will shut off and return to time t0 for another
delay cycle. The retry period is thus two dummy soft-start cycles
plus one variable (which depends on how long it takes to trip the
sensor each time). Figure 23 shows an example where the output
gets about half-way up before shutting down; therefore, the retry
(or hiccup) time will be around 17ms. The minimum should be
nominally 13.6ms and the maximum 20.4ms. If the short
condition is finally removed, the output should ramp up normally
on the next t2 cycle.
typical power supply to ramp up past 6.5V before the soft-start
ramps begins. This prevents a disturbance on the output, due to
the internal regulator turning on or off. If the transition is slow (not
a step change), the disturbance should be minimal. Thus, while the
recommendation is to not have the output enabled during the
transition through this region, it may be acceptable. The user
should monitor the output for their application to see if there is any
problem. If PVCC powers up first and VIN is not present by the time
the initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the VIN
ramp when it is applied. If this is not desired, then change the
sequencing of the supplies, or use the COMP/EN pin to disable
VOUT until both supplies are ready.
Figure 24 shows a simple sequencer for this situation. If PVCC
powers up first, Q1 will be off, and R3 pulling to PVCC will turn Q2
on, keeping the ISL8204M, ISL8206M in shutdown. When VIN
turns on, the resistor divider R1 and R2 determine when Q1 turns
on, which will turn off Q2 and release the shutdown. If VIN powers
up first, Q1 will be on, turning Q2 off; so the ISL8204M,
ISL8206M will start up as soon as PVCC comes up. The VENDIS trip
point is 0.4V nominal, so a wide variety of N-MOSFET or NPN BJT
or even some logic IC's can be used as Q1 or Q2. However, Q2
must be low leakage when off (open-drain or open-collector) so
as not to interfere with the COMP output. Q2 should also be
placed near the COMP/EN pin.
VIN
PVCC
T0
T1
T2
R3
R1
TO COMP/EN
~6.8ms ~6.8ms
VOUT
R2
Q1
Q2
FIGURE 23. OVERCURRENT RETRY OPERATION
Starting up into a shorted load looks the same as a retry into that
same shorted load. In both cases, OCP is always enabled during
soft-start; once it trips, it will go into retry (hiccup) mode. The
retry cycle will always have two dummy time-outs, plus whatever
fraction of the real soft-start time passes before the detection
and shutoff. At that point, the logic immediately starts a new two
dummy cycle time-out.
Input Voltage Considerations
Figure 16 shows a standard configuration where PVCC is either 5V
(±10%) or 12V (±20%). In each case, the gate drivers use the
PVCC voltage for low-side gate and high-side gate driver. In
addition, PVCC is allowed to work anywhere from 6.5V up to the
14.4V maximum. The PVCC range between 5.5V and 6.5V is not
allowed for long-term reliability reasons, but transitions through
it to voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias, which turns on between
5.5V and 6.5V. Some of the delay after POR is there to allow a
FIGURE 24. SEQUENCE CIRCUIT
The VIN range can be as low as ~1V (for VOUT as low as the 0.6V
reference) and as high as 20V. There are some restrictions for
running high VIN voltage. The maximum PHASE voltage is 30V.
VIN + PVCC + any ringing or other transients on the PHASE pin
must be less than 30V. If VIN is 20V, it is recommended to limit
PVCC to 5V.
Switching Frequency
The switching frequency is a fixed 600kHz clock, which is
determined by the internal oscillator. However, all of the other
timing mentioned (POR delay, OCP sample, soft-start, etc.) is
independent of the clock frequency (unless otherwise noted).
Selection of the Input Capacitor
The input filter capacitor should be based on how much ripple
the supply can tolerate on the DC input line. The larger the
capacitor, the less ripple expected but consideration should be
taken for the higher surge current during power-up. The
ISL8204M, ISL8206M provides the soft-start function that
FN6999 Rev 4.00
October 28, 2014
Page 13 of 19
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