LCMXO1200E-3TN100CES 查看數據表（PDF） - Lattice Semiconductor
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LCMXO1200E-3TN100CES Datasheet PDF : 95 Pages
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Lattice Semiconductor
Architecture
MachXO Family Data Sheet
Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices
Up to 9
4
Up to 6
Primary Clock 0
16:1
Primary Clock 1
16:1
Primary Clock 2
16:1
Primary Clock 3
16:1
Routing Clock PLL
Pads Outputs
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock
sources come from dual function clock pins and 12 come from internal routing.
Figure 2-9. Secondary Clocks for MachXO Devices
12
4
16:1
16:1
Secondary (Control)
Clocks
16:1
16:1
Routing Clock
Pads
2-8
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