TA16S1FAA 查看數據表（PDF） - Agere -> LSI Corporation

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TA16S1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

Data Sheet

March 2001

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Pin Descriptions (continued)

Table 3. TA16-Type Transponder Output Pin Descriptions

Pin Name

Pin Description

RxQ[0:15]P

RxQ[0:15]N

POCLKP

POCLKN

FP

SEARCH

LOS

LSRBIAS

LSRALRM

LPM

PCLKP/N

PHERR

IDPMON

LOCKDET

16-bit Differential LVPECL Parallel Output Data Bus. RxQ[0:15] is the

155 Mbyte/s 16-bit output word. RxQ15P/N is the most significant bit of the received

word and is the first bit serialized. RxQ00P/N is the least significant bit of the

received word and is the last bit serialized. RxQ[0:15]P/N is updated on the falling

edge of POCLk.

Differential LVPECL Parallel Output Clock. A 155 MHz nominally 50% duty cycle,

byte rate output clock that is aligned to the RxQ[0:15] byte serial output data.

RxQ[0:15] and FP are updated on the falling edge of POCLK.

Frame Pulse (LVPECL). Indicates frame boundaries in the received serial data

stream. If framing pattern detection is enabled (FRAMEN high and OOF), FP pulses

high for one POCLK cycle when a 32-bit sequence matching the framing pattern is

detected in the received serial data. FP is updated on the falling edge of POCLK.

A1 A2 Frame Search Output (LVTTL). A high on this output pin indicates that the

frame detection circuit is active and is searching for a new A1 A2 byte alignment.

This output will be high during the entire A1 A2 frame search. Once a new alignment

is found, this signal will remain high for a minimum of one 155 MHz clock period

beyond the third A2 byte before it will be set low.

Loss of Signal (LVTTL). A low on this output indicates a loss of lock by the clock

recovery circuit in the optical receiver.

Laser Bias (Analog). Provides an indication of the health of the laser in the trans-

mitter. This output changes at the rate of 20 mV/mA of bias current. If this output

voltage reaches 1.4 V (70 mA of bias), the automatic power control circuit is strug-

gling to maintain output power. This may indicate that the transmitter has reached an

end-of-life condition.

Laser Degrade Alarm (5 V CMOS). A logic low on this output indicates that the

transmitter’s automatic power control circuits are unable to maintain the nominal out-

put power. This output becomes active when the optical output power degrades 2 dB

below the nominal operating power.

Laser Power Monitor (Analog). Provides an indication of the output power level

from the transmitter laser. This output is set at 500 mV for the nominal transmitter

optical output power. If the optical power decreases by 3 dB, this output will drop to

approximately 250 mV, and if the output power should increase by 3 dB, this output

will increase to 1000 mV.

Parallel Byte Clock (Differential LVPECL). A byte-rate reference clock generated

by dividing the internal 2.488 GHz serial bit clock by 16. This output is normally used

to synchronize byte-wide transfers from upstream logic into the TA16 transponder.

See timing discussion for additional details, page 17.

Phase Error Signal (Single-Ended LVPECL). This signal pulses high during each

PCLK cycle for which there is potential setup/hold timing violations between the inter-

nal byte clock and the PICLK timing domains. PHERR is updated on the falling edge

of the PICLK output. For a detailed explanation, see the sectionon Transmitter Data

Input Timing on page 17.

Receiver Photodiode Current Monitor (Analog). This output provides a current

output that is a mirror of the photocurrent generated by the optical receiver’s photo-

diode (APD or PIN).

Lock Detect (LVTTL). This output goes low after the transmit side PLL has locked to

the clock signal provided at the TXREFCLK input pins. LOCKDET is an asynchronous

output.

Agere Systems Inc.

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